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this is information on a product in full production. october 2013 docid17928 rev 5 1/29 ST1S40 3 a dc step-down s witching regulator datasheet - production data features ? 3 a dc output current ? 4.0 v to 18 v input voltage ? output voltage adjustable from 0.8 v ? 850 khz switching frequency ? internal soft-start ? integrated 95 m ? and 69 m ? power mosfets ? all ceramic capacitor ? enable ? cycle-by-cycle current limiting ? current fold back short-circuit protection ? available in hsop-8, vfqfpn4x4-8l, and so8 packages applications ?? p/asic/dsp/fpga core and i/o supplies ? point of load for: stb, tvs, dvd ? optical storage, hard disk drive, printers, audio/graphic cards description the ST1S40 device is an internally compensated 850 khz fixed-frequency pwm synchronous step- down regulator. the ST1S40 operates from 4.0 v to 18 v input, while it re gulates an output voltage as low as 0.8 v and up to v in . the ST1S40 integrates a 95 m ? high side switch and 69 m ? synchronous rectifier allowing very high efficiency with very low output voltages. the peak current mode control with internal compensation delivers a very compact solution with a minimum component count. the ST1S40 is available in hsop-8, vfqfpn 4 mm x 4 mm - 8 lead, and standard so8 package. figure 1. application circuit vfqfpn 4 x 4 so8 hsop-8 9,16: 6: )% 3*1'$*1'h3dg (13* 676, &lqbvz ?) &rxw ?) /?+ 5 5 9,1$ &lqbd ?) 92879 9,1 9 www.st.com
contents ST1S40 2/29 docid17928 rev 5 contents 1 pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5.1 internal soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5.2 error amplifier and control loop stability . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5.3 overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.4 enable function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.5 hysteretic thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.1 input capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.2 inductor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.3 output capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.4 thermal dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.5 layout consideration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7 demonstration board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 8 typical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 9 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 10 order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 11 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
docid17928 rev 5 3/29 ST1S40 pin settings 29 1 pin settings 1.1 pin connection 1.2 pin description figure 2. pin connection (top view) 8 6 4 7 3 2 5 1 vina en fb gnd pgnd sw vinsw nc 8 45 1 vina en fb gnd pgnd sw vinsw agnd vfqfpn 8 6 4 7 3 2 5 1 vina en fb gnd pgnd sw vinsw nc hsop8 so8-bw 9 9 hsop-8 table 1. pin description no. type description vfqfpn and hsop-8 s08-bw 13 v ina unregulated dc input voltage 24en enable input. with en higher than 1.2 v the device in on and with en lower than 0.4 v the device is off (ST1S40ixx). 35fb feedback input. connecting the output vo ltage directly to this pin the output voltage is regulated at 0.8 v. to hav e higher regulated voltages an external resistor divider is required from vout to the fb pin. 4 6 agnd ground 5 - nc it can be connected to ground 6 8 vinsw power input voltage 7 1 sw regulator output switching pin 8 2 pgnd power ground - 7 ground 9 - epad exposed pad mandatory connected to ground
maximum ratings ST1S40 4/29 docid17928 rev 5 2 maximum ratings 3 thermal data table 2. absolute maximum ratings symbol parameter value unit v insw power input voltage -0.3 to 20 v v ina input voltage -0.3 to 20 v en enable voltage -0.3 to v ina v sw output switching voltage -1 to v in -2 v to -1 v for 50 nsec v fb feedback voltage -0.3 to 2.5 i fb fb current -1 to +1 ma p tot power dissipation at t a < 60 c 2.25 (hsop-8/dfn4x4); 1.6 so8-bw w t op operating junction temperature range -40 to 150 c t stg storage temperature range -55 to 150 c table 3. thermal data symbol parameter value unit r thja maximum thermal resist ance junction-ambient (1) 1. package mounted on the demonstration board. vfqfpn 40 c/w hsop-8 40 so8-bw 55
docid17928 rev 5 5/29 ST1S40 electrical characteristics 29 4 electrical characteristics t j = 25 c, v cc = 12 v, unless otherwise specified. table 4. electrical characteristics symbol parameter test condition values unit min. typ. max. v in operating input voltage range (1) 418 v v inon turn-on v cc threshold (1) 2.9 v inhys threshold hysteresis (1) 0.250 r dson -p high side switch on resistance i sw = 750 ma 95 m ? r dson -n low side switch on resistance i sw = 750 ma 69 m ? i lim maximum limiting current (2) 4.0 6.0 a oscillator f sw switching frequency 0.7 0.85 1 mhz d max maximum duty cycle (2) 100 % dynamic characteristics v fb feedback voltage 0.784 0.8 0.816 v (1) 0.776 0.8 0.824 %v out / ? i out reference load regulation isw = 10 ma to i lim (2) 0.5 % %v out / ? v in reference line regulation v in = 4.0 v to 18 v (2) 0.4 % dc characteristics i q quiescent current duty cycle = 0, no load v fb = 1.2 v 1.5 2.5 ma i qst-by total standby quiescent current off 2 15 ? a ifb fb bias current 50 enable v en en threshold voltage device on level 1.2 v device off level 0.4 i en en current 2 ? a
electrical characteristics ST1S40 6/29 docid17928 rev 5 soft start t ss soft-start duration 1 ms protection t shdn thermal shutdown 150 c hysteresis 15 1. specification referred to t j from -40 to +125 c. specifications in the -40 to +125 c temperature range are assured by design, characteriza tion and statistical correlation. 2. guaranteed by design. table 4. electrical characteristics (continued) symbol parameter test condition values unit min. typ. max.
docid17928 rev 5 7/29 ST1S40 functional description 29 5 functional description the ST1S40 device is based on a ?peak curren t mode?, constant frequency control. the output voltage v out is sensed by the feedback pin (fb) compared to an internal reference (0.8 v) providing an error signal that, compared to the output of the current sense amplifier, controls the on and off time of the power switch. the main internal blocks are shown in the block diagram in figure 3 . they are: ? a fully integrated osc illator that provides th e internal clock and th e ramp for the slope compensation avoiding sub-harmonic instability ? the soft-start circuitry to limit inrush current during the startup phase ? the transconductance error amplifier wit h integrated compensation network ? the pulse width modulator and the relative logic circuitry necessary to drive the internal power switches ? the drivers for embedded p-channel and n-channel power mosfet switches ? the high side current sensing block ? the low side current sense to implement diode emulation ? a voltage monitor circuitry (uvlo) that checks the input and internal voltages ? a thermal shutdown block, to prevent thermal run-away. figure 3. block diagram osc e/a driver driver dmd otp mosfet control logic regulator shut-down i_sense comp comp ocp ref 0.8v softstart vsum vc ocp uvlo vdrv_p vdrv_n i2v r sense vina vinsw sw gndp gnda en fb
functional description ST1S40 8/29 docid17928 rev 5 5.1 internal soft-start the soft-start is essential to assure correct a nd safe startup of the step-down converter. it avoids inrush current surge and causes the output voltage to increase monothonically. the soft-start is performed by ramping the non-inverting input (v ref ) of the error amplifier from 0 v to 0.8 v in around 1 ms. 5.2 error amplifier and control loop stability the error amplifier compares the fb pin volt age with the internal 0.8 v reference and it provides the error signal to be compared with t he output of the current sense circuitry, that is the high side power mosfet current. compari ng the output of the error amplifier and the peak inductor current implements the peak current mode control loop. the error amplifier is a transconductan ce amplifier (ota). the uncompensated characteristics are listed in table 5. table 5. error amplifier characteristics the ST1S40 device embeds the co mpensation network that assu res the stability of the loop in the whole operating range. all the tools needed to chec k the loop stability are shown below. parameter value dc gain 95 db gm 251 a/v ro 240 m ?
docid17928 rev 5 9/29 ST1S40 functional description 29 figure 4 shows the simple small signal model for the peak current mode control loop. figure 4. block diagram of the loop for the small signal analysis three main terms can be identified to obtain the loop transfer function: 1. from control (output of e/a) to output, g co (s) 2. from output (vout) to the fb pin, g div (s) 3. from the fb pin to control (output of e/a), g ea (s). the transfer function from control to output g co (s) results: equation 1 where r load represents the load resistance, r i (0.3 ? ) the equivalent sensing resistor of the current sense circuitry, ? p the single pole introduced by the lc filter and ? z the zero given by the esr of the output capacitor. f h (s) accounts for the sampling effect performe d by the pwm comparator on the output of the error amplifier that introduces a double pole at one half of the switching frequency. equation 2 l cout current sense logic and driver slope com pensation pw m com parator error amp rc cc r1 r2 0.8 v high side switch low side switch g co (s) g div (s) g ea (s) vin v c v out v fb g co s ?? r load r i ----------------- - 1 1 r out t sw ? l --------------------------- - m c 1d ? ?? 0.5 ? ? ?? ? + -------------------------------------------------------------------------------------------- - 1 s ? z ------ + ?? ?? 1 s ? p ------ + ?? ?? --------------------- - f h s ?? ??? = ? z 1 esr c out ? ------------------------------- =
functional description ST1S40 10/29 docid17928 rev 5 equation 3 where: equation 4 s n represents the on time slope of the sensed inductor current, s e the slope of the external ramp (v pp peak-to-peak amplitude 1.25 v) that implements the slope compensation to avoid sub-harmonic oscillation s at duty cycle over 50%. the sampling effect contribution f h (s) is: equation 5 where: equation 6 and equation 7 the resistor to adjust the output voltage gives the term from output voltage to the fb pin. g div (s) is: the transfer function from fb to vcc (output of e/a) introduces the singularities (poles and zeros) to stab ilize the loop. figure 5 shows the small signal model of the error amplifier with the internal compensation network. ? p 1 r load c out ? ------------------------------------- - m c 1d ? ?? 0.5 ? ? lc out f sw ?? --------------------------------------------- + = m c 1 s e s n ------ + = s e v pp f sw ? = s n v in v out ? l ----------------------------- - r i ? = ? ? ? ? ? ? ? ? ?? 1 1 s ? n q p ? ------------------ - s 2 ? n 2 ------ ++ ------------------------------------------ - = q p 1 ? m c 1d ? ?? 0.5 ? ? ?? ? ---------------------------------------------------------- = ? n ? f sw ? = g div s ?? r 2 r 1 r 2 + -------------------- =
docid17928 rev 5 11/29 ST1S40 functional description 29 figure 5. small signal model for the error amplifier r c and c c introduce a pole and a zero in the open loop gain. c p does not significantly affect system stability and can be neglected. so g ea (s) results: equation 8 where g ea = g m r o the poles of this transfer function are (if c c >> c 0 +c p ): equation 9 equation 10 whereas the zero is defined as: equation 11 the embedded compensation network is r c = 70 k ? , c c = 195 pf while c p and c o can be considered as negligible. the error amplifier output resistance is 240 m ?? so the relevant singularities are: equation 12 &r 5r &f 5f &s *p 9g 9 )% 9 5() 9g g ea s ?? g ea0 1s + r c c c ?? ?? ? s 2 r 0 c 0 c p + ?? r c c c sr 0 c c ? r 0 c 0 c p + ?? r c c c ? + ? + ?? 1 + ? + ?? ?? ------------------------------------------------------------------------------------------------------------------------------- ---------------------------------------------------------- = f p lf 1 2 ? r 0 c c ?? ? --------------------------------- - = f p hf 1 2 ? r c c 0 c p + ?? ?? ? ---------------------------------------------------- = f z 1 2 ? r c c c ?? ? --------------------------------- = f z 11 6 khz ? = f p lf 34 hz ? =
functional description ST1S40 12/29 docid17928 rev 5 so by closing the loop, the loop gain g loop (s) is: equation 13 example: vin = 12 v, vout = 1.2 v, iomax = 3 a, l = 1.5 h, cout = 47 f (mlcc), r1 = 10 k ? , r2 = 20 k ?? (see section 6.2 and section 6.3 for inductor and output capacitor selection guidelines). the module and phase bode plot are reported in figure 6. the bandwidth is 100 khz and the phase margin is 45 degrees. figure 6. module and phase bode plot g loop s ?? g co s ?? g div s ?? g ea s ?? ?? =
docid17928 rev 5 13/29 ST1S40 functional description 29 5.3 overcurrent protection the ST1S40 device implements the pulse-by-pulse overcurrent protection. the peak current is sensed through the high side power mosfet and when it exceeds the first overcurrent threshold (ocp1) the high side is immediately turned off and the low side conducts the inductor current for the rest of the clock period. during overload condition, since the duty cycle is not set by the control loop but is limited by the overcurrent threshold, the output voltage dr ops out of regulation. if the feedback falls below 0.3 v the switching frequency is reduced to one fourth and the current limit threshold is folded back to around 2 a. thanks to the current and freq uency fold back the stress on the device and on the external power components is reduced in case of severe overload or dead-short to ground of the output. the current fold back is disabled during the startup, in order to allow the vout to rise up properly in case of the big output capacitor requiring high extra current to be charged. an additional mechanism is protecting the device in case of short-circ uit on the output and high input voltage. a further threshold (ocp2, 1a higher than ocp1) is compared to the inductor current. if the inductor current exceeds ocp2, the device stops switching and restarts with a soft-start cycle. 5.4 enable function the enable feature allows the device to be put into standby mode. with the en pin lower than 0.4 v, the device is disabled and the pow er consumption is reduced to less than 15 a. with the en pin higher than 1.2 v, the device is enabled. if the en pin is left floating, an internal pull-down ensures that the voltage at the pin reaches the inhibit threshold and the device is disabled. the pin is also v in compatible. 5.5 hysteretic thermal shutdown the thermal shutdown block generates a signal that turns off the power stage if the junction temperature goes above 150 ? c. once the junction temperature goes back to about 130 ? c, the device restarts in normal operation.
application information ST1S40 14/29 docid17928 rev 5 6 application information 6.1 input capacitor selection the capacitor connected to the input must be capable of supporting the maximum input operating voltage and the maximum rms input current required by the device. the input capacitor is subject to a pulsed current, the rm s value of which is dissipated over its esr, affecting the overa ll system efficiency. so the input capacitor must have an rms current rating higher than the maximum rms input current and an esr value compliant with the expected efficiency. the maximum rms input current flowing through the capacitor can be calculated as: equation 14 where io is the maximum dc outpu t current, d is th e duty cycle, ?? is the efficiency. considering ????? , this function has a maximum at d = 0.5 and is equal to io/2. the peak-to-peak voltage across the input capacitor can be calculated as: equation 15 where esr is the equivalent series resistance of the capacitor. given the physical dimension, ceramic capaci tors can well meet the requirements of the input filter sustaining a higher input rms curren t than electrolytic / tantalum types. in this case the equation of c in as a function of the target peak-to-peak voltage ripple (v pp ) can be written as follows: equation 16 neglecting the small esr of ceramic capacitors. considering ?? = 1, this function has its maximum in d = 0.5, therefore, given the maximum peak-to-peak input voltage (v pp_max ), the minimum input capacitor (c in_min ) value is: equation 17 typically, c in is dimensioned to keep the maximum peak -to-peak voltage ripple in the order of 1% of v inmax . i rms i o d 2d 2 ? ? -------------- - ? d 2 ? 2 ------ - + ? = v pp i o c in f sw ? ------------------------- 1 d ? --- - ? ?? ?? d d ? --- - 1d ? ?? ? + ? esr i o ? + ? = c in i o v pp f sw ? -------------------------- - 1 d ? --- - ? ?? ?? d d ? --- - 1d ? ?? ? + ? ? = c in_min i o 2v pp_max f sw ?? ----------------------------------------------- - =
docid17928 rev 5 15/29 ST1S40 application information 29 in table 6 some multi layer ceramic capacitors su itable for this device are reported. a ceramic bypass capacitor, as close as possible to the v ina pin, so that additional parasitic esr and esl are minimized, is suggested in order to prevent inst ability on the output voltage due to noise. the value of the bypass capacitor can go from 330 nf to 1 f. 6.2 inductor selection the inductance value fixes the current ripple flowing through the output capacitor. so the minimum inductance value, to have the expected current ripple, must be selected. the rule to fix the current ripple value is to have a ripple at 20% to 40% of the output current. in continuous current mode (ccm), the inductance value can be calculated by equation 18 equation 18 where t on is the conduction time of the high side switch and t off is the conduction time of the low side switch (in ccm, f sw = 1/(t on + t off )). the maximum current ripple, given the vout, is obtained at maximum t off , that is at minimum duty cycle. so by fixing ? i l = 20% to 30% of the maximum output current, the minimum inductance value can be calculated: equation 19 where f swmin is the minimum switching frequency, according to table 4 the peak current through the inductor is given by: equation 20 so if the inductor value decreases, the peak curr ent (that must be lower than the current limit of the device) increases. the higher the induct or value, the higher the average output current that can be delivered, without reaching the current limit. table 6. input mlcc capacitors manufacturer series cap value ( ? f) rated voltage (v) murata grm31 10 25 grm55 10 25 tdk c3225 10 25 ? i l v in v out ? l ----------------------------- - t on ? v out l -------------- t off ? == l min v out ? i max ---------------- 1d min ? f swmin ---------------------- - ? = i lpk ? i o ? i l 2 -------- + =
application information ST1S40 16/29 docid17928 rev 5 in table 7 below some inductor part numbers are listed. 6.3 output capacitor selection the current in the output capacitor has a triangular waveform which generates a voltage ripple across it. this ripple is due to the ca pacitive component (charge or discharge of the output capacitor) and the resistive component ( due to the voltage drop across its esr). so the output capacitor must be selected in order to have a voltage ripple compliant with the application requirements. the amount of the voltage ripple can be calculated starting from the current ripple obtained by the inductor selection. equation 21 for ceramic (mlcc) capacitors the capacitive component of the ripple dominates the resistive one. whilst for electrolytic capacitors the opposite is true. since the compensation network is internal, the output capacitor should be selected in order to have a proper phase margin and then a stable control loop. the equations of section 5.2 help to check loop stability given the applicat ion conditions, the value of the inductor, and of the output capacitor. in table 8 some capacitor series are listed. table 7. inductors manufacturer series inductor value ( ? h) saturation current (a) coilcraft xpl7030 2.2 to 4.7 6.8 to 10.5 mss1048 2.2 to 6.8 4.14 to 6.62 mss1260 10 5.5 wurth we-hc/hca 3.3 to 4.7 7 to 11 we-tpc typ xlh 3.6 to 6.2 4.5 to 6.4 we-pd type l 10 5.6 tdk rlf7030t 2.2 to 4.7 4 to 6 table 8. output capacitors manufacturer series cap value ( ? f) rated voltage (v) esr (m ? ) murata grm32 22 to 100 6.3 to 25 < 5 grm31 10 to 47 6.3 to 25 < 5 panasonic ecj 10 to 22 6.3 < 5 eefcd 10 to 68 6.3 15 to 55 sanyo tpa/b/c 100 to 470 4 to 16 40 to 80 tdk c3225 22 to 100 6.3 < 5 ? v out esr ? i max ? ? i max 8c out f sw ?? ------------------------------------ - + =
docid17928 rev 5 17/29 ST1S40 application information 29 6.4 thermal dissipation the thermal design is important in order to prevent thermal shutdown of the device if junction temperature goes above 150 c. the three different sources of losses within the device are: a) conduction losses due to the on resistance of high side switch (r hs ) and low side switch (r ls ); these are equal to: equation 22 where d is the duty cycle of the application. note that the duty cycle is theoretically given by the ratio between v out and v in , but is actually slightly highe r to compensate the losses of the regulator. b) switching losses due to high side power mosfet turn on and off; these can be calculated as: equation 23 where t rise and t fall are the overlap times of the vo ltage across the high side power switch (v ds ) and the current flowing into it during turn on and turn off phases, as shown in figure 7 . t sw is the equivalent switching time. fo r this device the typical value for the equivalent switching time is 20 ns. c) quiescent current lo sses, calculated as: equation 24 where i q is the quiescent current (i q = 2.5 ma maximum). the junction temperature t j can be calculated as: equation 25 where t a is the ambient temperature and p tot is the sum of the power losses just seen. rth ja is the equivalent thermal resistance junction to ambient of the device; it can be calculated as the parallel of many paths of heat conduction from the junction to the ambient. for this device the path through the exposed pa d is the one conducting the largest amount of heat. the rth ja measured on the demonstration board described in the following paragraph is about 40 c/w for the vfqfpn and hsop packages and about 55 c/w for the so8-bw package. p cond r hs i out 2 dr ls i out 2 1d ? ?? ?? + ?? = p sw v in i out t rise t fall + ?? 2 ------------------------------------------ - fsw ?? ? v in i out t sw f sw ??? == p q v in i q ? = t j t a rth ja p tot ? + =
application information ST1S40 18/29 docid17928 rev 5 figure 7. switching losses 6.5 layout consideration the pc board layout of switching dc-dc regulato r is very important in order to minimize the noise injected in high impedance nodes, to reduce interferences generated by the high switching current loops, and to opti mize the reliability of the device. in order to avoid emc problems, the high switching current loops must be as short as possible. in the buck converter there are two high switching current loops: during the on time, the pulsed current flows through the inpu t capacitor, the high side power switch, the inductor and the output capacitor; during the off time, through the low side power switch, the inductor and the output capacitor. the input capacitor connected to vinsw must be placed as close as possible to the device, to avoid spikes on vinsw due to the st ray inductance and the pulsed input current. in order to prevent dynamic unbalance between vinsw and v ina , the trace connecting the v ina pin to the input must be derived from vinsw. the feedback pin (fb) connection to the external resistor divider is a high impedance node, so the interferences can be minimized through the routing of the feedback node with a very short trace and as far as possible from the high current paths. a single point connection from signal gr ound to power ground is suggested. thanks to the exposed pad of the device, the ground plane helps to reduce the thermal resistance junction to ambient; so a large gr ound plane, soldered to the exposed pad, enhances the thermal performance of the converter allowing high power conversion. v sw i sw,hs v in v ds,hs p cond,hs p cond,ls p sw t fall t rise
docid17928 rev 5 19/29 ST1S40 application information 29 figure 8. pcb layout guidelines input cap as close as possible to vinsw pin star center for common ground short fb trace vina derived from cin to avoid dynamic voltage drop between vina and vinsw short high switching current loop via to connect the thermal pad to bottom or inner ground plane
demonstration board ST1S40 20/29 docid17928 rev 5 7 demonstration board figure 9. demonstration boards schematic table 9. component list reference part number description manufacturer u1 ST1S40 stmicroelectronics ? l1 dra74 3r3 3.3 h, isat = 5.4 a coiltronics c1 c3225x7re106k 10 f 25 v x7r tdk c2 c3225x7r1c226m 22 f 16 v x7r tdk c3 1 f 25 v x7r c4 nc r1 62.5 k ? r2 20 k ? r3 10 k ?
docid17928 rev 5 21/29 ST1S40 demonstration board 29 figure 10. demonstration board pcb top and bottom: hsop-8 package figure 11. demonstration board pcb top and bottom: vfqfpn package figure 12. demonstration board pcb top and bottom: so8-bw package
typical characteristics ST1S40 22/29 docid17928 rev 5 8 typical characteristics figure 13. efficiency vs. i out figure 14. efficiency vs. i out 40 50 60 70 80 90 100 0.00 0.50 1.00 1.50 2.00 2.50 3.00 efficiency ? [%] iout ? [a] vin=5v vo=3.3v vo=1.8v vo=1.2v 40 45 50 55 60 65 70 75 80 85 90 0.00 0.50 1.00 1.50 2.00 2.50 3.00 efficiency ? [%] iout ? [a] vin=12v vo=1.8v vo=1.2v figure 15. efficiency vs. i out figure 16. overcurrent protection 40 50 60 70 80 90 100 0.00 0.50 1.00 1.50 2.00 2.50 3.00 efficiency ? [%] iout ? [a] vin=12v vo=5v vo=3.3v figure 17. short-circuit protection figure 18. so8-bw maximum i out ta m b = 6 0 d e g c tjmax=150degc maximum i out according to 1.6w power dissipation limit with so8-bw package
docid17928 rev 5 23/29 ST1S40 package information 29 9 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack specifications, grade definitions a nd product status are available at: www.st.com . ecopack is an st trademark.
package information ST1S40 24/29 docid17928 rev 5 figure 19. vfqfpn8 (4 x 4 x 1.0 mm) package outline table 10. vfqfpn8 (4 x 4 x 1.0 mm) package mechanical data symbol dimensions mm inch min. typ. max. min. typ. max. a 0.80 0.90 1.00 0.0315 0.0354 0.0394 a1 0.02 0.05 0.0008 0.0020 a3 0.20 0.0079 b 0.23 0.30 0.38 0.009 0.0117 0.0149 d 3.90 4.00 4.10 0.153 0.157 0.161 d2 2.82 3.00 3.23 0.111 0.118 0.127 e 3.90 4.00 4.10 0.153 0.157 0.161 e2 2.05 2.20 2.30 0.081 0.087 0.091 e 0.80 0.031 l 0.40 0.50 0.60 0.016 0.020 0.024 %
docid17928 rev 5 25/29 ST1S40 package information 29 figure 20. so8-bw package outline table 11. so8-bw package mechanical data symbol dimensions mm inch min. typ. max. min. typ. max. a 135 1.75 0.053 0.069 a1 0.10 0.25 0.004 0.001 a2 1.10 1.65 0.043 0.065 b 0.33 0.51 0.013 0.020 c 0.19 0.25 0.007 0.01 d (1) 1. dimension d does not include mold fl ash, protrusions or gate burrs. mold flash, protrusions or gate burrs must not exceed 0.15 mm (.006 inch) in total (both sides). 4.80 5.00 0.1890 0.1929 0.1969 e 3.80 4.00 0.15 0.157 e 1.27 0.050 h 5.80 6.20 0.228 0.244 h 0.25 0.50 0.0098 0.0197 l 0.40 1.27 0.0157 0.0500 k 0(min.), 8 (max.) ddd 0.10 0.0039 n k[? ( h $ $ % ' + / & 6hdwlqj 3odqh pp *djh3odqh $ ggg& &
package information ST1S40 26/29 docid17928 rev 5 figure 21. hsop-8 package outline ' pp7\s ( pp7\s $0y
docid17928 rev 5 27/29 ST1S40 package information 29 table 12. hsop-8 package mechanical data symbol dimensions mm inch min. typ. max. min. typ. max. a 1.70 0.0669 a1 0.00 0.150 0.00 0.0059 a2 1.25 0.0492 b 0.31 0.51 0.0122 0.0201 c 0.17 0.25 0.0067 0.0098 d 4.80 4.90 5.00 0.1890 0.1929 0.1969 e 5.80 6.00 6.20 0.2283 0.2362 0.2441 e1 3.80 3.90 4.00 0.1496 0.1535 0.1575 e1.27 0.0500 h 0.25 0.50 0.0098 0.0197 l 0.40 1.27 0.0157 0.0500 k 0.00 8.00 0.3150 ccc 0.10 0.0039
order codes ST1S40 28/29 docid17928 rev 5 10 order codes 11 revision history table 13. ordering information order codes package function ST1S40ipur vfqfpn 4 x 4 8l enable ST1S40iphr hsop-8 ST1S40idr so8-bw table 14. document revision history date revision changes 15-dec-2010 1 first release 04-mar-2011 2 updated: ta ble 1 , ta ble 2 , table 3 and ta ble 13 . 20-dec-2011 3 updated cover page: table 1 , table 2 , section 5 added section 6 , section 7 and section 8 01-mar-2012 4 hsop8 mechanical data and package dimensions have been updated. 10-oct-2013 5 updated table 2 - added value ?-2 v to -1 v for 50 nsec? for parameter v sw . reformatted section 9: package information - reversed order of figure 19 and table 10 , figure 20 and table 11 , figure 21 and table 12 . minor corrections throughout document.
docid17928 rev 5 29/29 ST1S40 29 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. st products are not designed or authorized for use in: (a) safety critical applications such as life supporting, active implanted devices or systems wi th product functional safety requirements; (b) aeronautic applications; (c) automotive applications or environments, and/or (d) aerospace applications or environments. where st products are not designed for such use, the purchaser shall use products at purchaser?s sole risk, even if st has been informed in writing of such usage, unless a product is expressly designated by st as being intended for ?automotive, automotive safety or medical? industry domains according to st product design specifications. products formally escc, qml or jan qualified are deemed suitable for use in aerospace by the corresponding governmental agency. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2013 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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